Processors often use virtual memory to store and retrieve data. Virtual memory enables data to have consecutive virtual memory addresses while being stored in various physical memory addresses that may not be continuous, and in more than one physical memory. The data may be accessed by translation of an associated virtual memory address to a corresponding physical memory address through use of a translation lookaside buffer (TLB). Virtual addresses also enable multiple processes to run in parallel where the program code from different processes use the same virtual addresses but the TLB maps the accesses to distinct physical address spaces.
In some computation scenarios, correspondence between virtual memory addresses and physical memory addresses may change, due to e.g., remap of the TLB, access restriction imposed on a portion of the data, change of context (e.g., use of the TLB by several different programs), etc. Typically, such changes in the contents of the TLB necessitate a flush of a cache memory and re-installation of data in the cache memory, which can be a time consuming and processor-intensive process, and can cause execution of instructions by the processor to be halted while the cache flush is conducted.